While ΣΔM techniques are applied widely in analog conversion sub-systems, both analog-to-digital (ADC) and digital-to-analog (DAC) converters, these methods have enjoyed much less exposure in the broader application domain, where flexible and configurable solutions, traditionally supplied via a software DSP (soft-DSP), are required. And this limited level of exposure is easy to understand. Most, if not all, of the efficiencies and optimizations afforded by ΣΔM are hardware oriented and so cannot be capitalized on in the fixed precision pre-defined datapath found in a soft-DSP processor. This limitation, of course, does not exist in a field programmable gate array (FPGA) DSP solution. With FPGAs the designer has complete control of the silicon to implement any desired datapath and employ optimal word precisions in the system with the objective of producing a design that satisfies the specifications in the most economically sensitive manner.
While implementation of a digital ΣΔ ASIC (application-specific integrated circuit) is of course possible, economic constraints make the implementation of such a building block that would provide the flexibility, and be generic enough to cover a broad market cross-section, impractical. FPGA-based hardware provides a solution to this problem. FPGAs are off-the-shelf commodity items that provide a silicon feature set ideal for constructing high-performance DSP systems. These devices maintain the flexibility of software-based solutions, while providing levels of performance that match, and often exceed, ASIC solutions.
There is a rich and expanding body of literature devoted to the efficient and effective implementation of digital signal processors using FPGA based hardware. More often than not, the most successful of these techniques involves a paradigm shift away from the methods that provide good solutions in software programmable DSP systems.
Semiconductor vendors, such as Xilinx, Altera, Atmel, and AT&T, provide a range of FPGAs. The architectural approaches are as diverse as there are manufacturers, but some generalizations can be made. Most of the devices are basically organized as an array of logic elements and programmable routing resources used to provide the connectivity between the logic elements, FPGA I/O pins and other resources, such as on-chip memory. The structure and complexity of the logic elements, as well as the organization and functionality supported by the interconnection hierarchy, distinguish the devices. Other device features, such as block memory and delay locked loop technology, are also significant factors that influence the complexity and performance of an algorithm that is implemented using FPGAs.
A logic element usually consists of one or more RAM (random access memory) n-input look-up tables, where n is between 3 and 6, in one to several flip-flops. There may also be additional hardware support in each element to enable high-speed arithmetic operations. This generic FPGA architecture is shown in FIG. 1. Also illustrated in the Figure (as wide lines) are several connections between logic elements and the device input/output (I/O) ports. Application-specific circuitry is supported in the device by downloading a bit stream into SRAM (static random access memory) based configuration memory. This personalization database defines the functionality of the logic elements, as well as the internal routing. Different applications are supported on the same FPGA hardware platform by configuring the FPGA(s) with appropriate bit streams. As a specific example, consider the Xilinx Virtex™ series of FPGAs. The logic elements, called slices, essentially consist of two four-input look-up tables (LUTs), two flip-flops, several multiplexors and some additional silicon support that allows the efficient implementation of carry-chains for building high-speed adders, subtracters, and shift registers. Two slices form a configurable logic block (CLB) as shown in FIG. 2. The CLB is the basic tile that is used to build the logic matrix. Some FPGAs, like the Xilinx Virtex families, supplying on-chip block RAM. FIG. 3 shows the CLB matrix that defines a Virtex FPGA. Current generation Virtex silicon provides a family of devices offering 768 to 12,288 logic slices, and from 8 to 32 variable form factor block memories.
Xilinx XC4000 and Virtex devices also allow the designer to use the logic element LUTs as memory, either ROM or RAM. Constructing memory with this distributed memory approach can yield access bandwidths in many tens of gigabytes per second range.
Typical clock frequencies for current generation devices are in the multiple tenants of megahertz (100 to 200) range.
In contrast to the logic slice architecture employed in Xilinx Virtex devices, a logic block architecture employed in the Atmel AT40K FPGA is shown in FIG. 4. Like the Xilinx device, combinational logic is realized using look-up tables. In this case, two three-input LUTs and a single flip-flop are available in each logic cell. The pass gates in a cell form part of the signal routing network and are used for connecting signals to the multiple horizontal and vertical bus planes. In addition to the orthogonal routing resources, indicated as N, S, E and W in FIG. 4, a diagonal group of interconnects (NW, NE, SE, and SW), associated with each cell x output, are available to provide efficient connections to neighboring cell's x bus inputs.
The objective of the FPGA/DSP architect is to formulate algorithmic solutions for applications that best utilize FPGA resources to achieve the required functionality. This is a three-dimensional optimization problem in power, complexity, and bandwidth. The remainder of this application describes some novel FPGA solutions to several signal processing problems. The results are important in an industrial context because they enable either smaller, and hence more economic, solutions to important problems, or allow more arithmetic compute power to be realized with a given area of silicon.
ΣΔ Modulation
Sigma-Delta modulation is a source coding technique most prominently employed in analog-to-digital and digital-to-analog converters. In this context, hybrid analog and digital circuits are used in the realization. FIG. 5 shows a single-loop ΣΔ modulator. Provided the input signal is busy enough, the linearized discrete time model of FIG. 6 can be used to illustrate the principle. In FIG. 6, the 1-bit quantizer is modeled by an additive white noise source with variance σe2=Δ2/12, where Δ represents the quantization interval. The z-transform of the system is                                                                         Y                ⁡                                  (                  z                  )                                            =                                                                                          H                      ⁡                                              (                        z                        )                                                                                    1                      +                                              H                        ⁡                                                  (                          z                          )                                                                                                      ⁢                                      X                    ⁡                                          (                      z                      )                                                                      +                                                      1                                          1                      +                                              H                        ⁡                                                  (                          z                          )                                                                                                      ⁢                                      Q                    ⁡                                          (                      z                      )                                                                                                                                              =                                                                                          H                      s                                        ⁡                                          (                      z                      )                                                        ⁢                                      X                    ⁡                                          (                      z                      )                                                                      +                                                                            H                      n                                        ⁡                                          (                      z                      )                                                        ⁢                                      Q                    ⁡                                          (                      z                      )                                                                                                                              Equations        ⁢                                   ⁢        1        ⁢                                   ⁢        and        ⁢                                   ⁢        2            where                               H          ⁡                      (            z            )                          =                  1                      z            -            1                                              Equation        ⁢                                   ⁢        3            which is the transfer function of delay and an ideal integrator, and Hs(z) and Hn(z) are the signal and noise transfer functions (NTF) respectively. In a good ΣΔ modulator, Hn(ω) will have a flat frequency response in the interval |f|≦B. In contrast, Hn(ω) will have a high attenuation in the frequency band |f|≦B and a “don't care” region in the interval B<|f|<fs/2. For the single loop ΣΔ in FIG. 6, Hs(z)=z−1 and Hn(z)=1−z−1. Thus the input signal is not distorted in any way by the network and simply experiences a pure delay from input to output. The performance of the system is determined by the noise transfer function Hn(z), which is given by                                                                   H              n                        ⁡                          (              f              )                                                =                  4          ⁢                                                sin              ⁢                                                π                  ⁢                                                                           ⁢                  f                                                  f                  s                                                                                                    Equation        ⁢                                   ⁢        4            and is shown in FIG. 7. The in-band quantization noise variance is                               σ          n          2                =                              ∫                          -              B                                      +              B                                ⁢                                                                                                          H                    n                                    ⁡                                      (                    f                    )                                                                              2                        ⁢                                          S                q                            ⁡                              (                f                )                                      ⁢                          ⅆ              f                                                          Equation        ⁢                                   ⁢        5            where Sq(f)=σq2/fs is the power spectral density of the quantization noise. Observe that for a non-shaped noise (or white) spectrum, increasing the sampling rate by a factor of 2, while keeping the bandwidth B fixed, reduces the quantization noise by 3 dB. For a first order ΣΔM it can be shown that                               σ          n          2                ≈                              1            3                    ⁢                      π            2                    ⁢                                                    σ                q                2                            ⁡                              (                                                      2                    ⁢                                                                                   ⁢                    B                                                        f                    s                                                  )                                      3                                              Equation        ⁢                                   ⁢        6            for fx>>2B. Under these conditions doubling the sampling frequency reduces the noise power by 9 dB, of which 3 dB is due to the reduction in Sq(f) and a further 6 dB is due to the filter characteristic Hn(f). The noise power is reduced by increasing the sampling rate to spread the quantization noise over a large bandwidth and then by shaping the power spectrum using an appropriate filter.Reduced Complexity Filters Using ΣΔ Modulation Techniques
ΣΔM techniques can be employed for realizing area efficient narrowband filters in FPGAs. These filters are utilized in many applications. For example, narrow-band communication receivers, multi-channel RF surveillance systems and for solving some spectrum management problems.
A uniform quantizer operating at the Nyquist rate is the standard solution to the problem of representing data within a specified dynamic range. Each additional bit of resolution in the quantizer provides an increase in dynamic range of approximately 6 dB. A signal with 60 dB of dynamic range requires 10 bits, while 16 bits can represent data with a dynamic range of 96 dB.
While the required dynamic range of a system fixes the number of bits required to represent the data, it also affects the expense of subsequent arithmetic operations, in particular multiplications. In any hardware implementation, and of course this includes FPGA based DSP processors, there are strong economic imperatives to minimize the number and complexity of the arithmetic components employed in the datapath. An embodiment of the invention employs noise-shaping techniques to reduce the precision of the input data samples to minimize the complexity of the multiply-accumulate (MAC) units in the filter. The net result is a reduction in the amount of FPGA logic resources required to realize the specified filter.
Consider the structure shown in FIG. 8. Instead of applying the quantized data x(n) from the analog-to-digital converter directly to the filter, data x(n) is pre-processed by a ΣΔ modulator. The re-quantized input samples {circumflex over (x)}(n) are represented using fewer bits per sample, so permitting the subsequent filter H(z) to employ reduced precision multipliers in the mechanization. The filter coefficients are still kept to a high precision.
The ΣΔ data re-quantizer is based on a single loop error feedback sigma-delta modulator shown in FIG. 9. In this configuration, the difference between the quantizer input and output sample is a measure of the quantization error, which is fed back and combined with the next input sample. The error-feedback sigma-delta modulator operates on a highly oversampled input and uses the unit delay z-1 as a predictor. With this basic error-feedback modulator, only a small fraction of the bandwidth can be occupied by the required signal. In addition, the circuit only operates at baseband. A larger fraction of the Nyquist bandwidth can be made available and the modulator can be tuned if a more sophisticated error predictor is employed. This requires replacing the unit delay with a prediction filter P(z). This generalized modulator is shown in FIG. 10.
The operation of the re-quantizer can be understood by considering the transform domain description of the circuit. This is expressed as{circumflex over (X)}(z)=X(z)+Q(z)(1−P(z)z−1)  Equation 7 where Q(z) is the z-transform of the equivalent noise source added by the quantizer q(•), P(z) is the transfer function of the error predictor filter, and X(z) and {circumflex over (X)}(z) are the transforms of the system input and output respectively. P(z) is designed to have unity gain and leading phase shift in the bandwidth of interest. Within the design bandwidth, the term Q(z)(1−P(z)z−1)=0 and so X(z)={circumflex over (X)}(z). By designing P(z) to be commensurate with the system passband specifications, the in-band spectrum of the re-quantizer output will ideally be the same as the corresponding spectral region of the input signal.
To illustrate the operation of the system consider the task of recovering a signal that occupies 10% of the available bandwidth and is centered at a normalized frequency of 0.3 Hz. The stopband requirement is to provide 60 dB of attenuation. FIG. 11A shows the input test signal. It comprises an in-band component and two out-of-band tones that are to be rejected. FIG. 11B is a frequency domain plot of the signal after it has been re-quantized to 4 bits of precision by a ΣΔ modulator employing an 8th order predictor in the feedback path. Notice that the 60 dB dynamic range requirement is supported in the bandwidth of interest, but that the out-of-band SNR has been compromised. This is of course acceptable, since the subsequent filtering operation will provide the necessary rejection. A 160-tap filter H(z) satisfies the problem specifications. The frequency response of H(z) using 12-bit filter coefficients is shown in FIG. 11C. Finally, H(z) is applied to the reduced sample precision data stream {circumflex over (X)}(z) to produce the spectrum shown in FIG. 11D. Observe that the desired tone has been recovered, the two out-of-band components have been rejected, and that the in-band dynamic range meets the 60 dB requirement.
Prediction Filter Design
The design of the error predictor filter is a signal estimation problem. The optimum predictor is designed from a statistical viewpoint. The optimization criterion is based on the minimization of the mean-squared error. As a consequence, only the second-order statistics (autocorrelation function) of a stationary process are required in the determination of the filter. The error predictor filter is designed to predict samples of a band-limited white noise process Nxx(ω) shown in FIG. 12. Nxx(ω) is defined as:                                           N            xx                    ⁡                      (            ω            )                          =                  {                                                    1                                                                                  -                    θ                                    ≤                  ω                  ≤                  θ                                                                                    0                                            otherwise                                                                        Equation        ⁢                                   ⁢        8            and related to the autocorrelation sequence rxx(m) by discrete-time Fourier transform (DTFT).                                           N            xx                    ⁡                      (            ω            )                          =                              ∑                          n              =                              -                ∞                                      ∞                    ⁢                                                    r                xx                            ⁡                              (                k                )                                      ⁢                          ⅇ                                                -                  j                                ⁢                                                                   ⁢                w                ⁢                                                                   ⁢                n                                                                        Equation        ⁢                                   ⁢        9            The autocorrelation function rxx(n) is found by taking the inverse DTFT of the equation immediately above.                                           r            xx                    ⁡                      (            n            )                          =                              1                          2              ⁢                                                           ⁢              π                                ⁢                                    ∫                              -                π                            π                        ⁢                                                            N                  xx                                ⁡                                  (                  ω                  )                                            ⁢                              ⅇ                                                      -                    j                                    ⁢                                                                           ⁢                  ω                  ⁢                                                                           ⁢                  n                                            ⁢                              ⅆ                ω                                                                        Equation        ⁢                                   ⁢        10            Nxx(ω) is non-zero only in the interval −θ≦ω≦θ giving rxx(n) as:                                           r            xx                    ⁡                      (            n            )                          =                              θ            π                    ⁢          sin          ⁢                                           ⁢                      c            ⁡                          (                              θ                ⁢                                                                   ⁢                n                            )                                                          Equation        ⁢                                   ⁢        11            
So the autocorrelation function corresponding to a band-limited white noise power spectrum is a sinc function. Samples of this function are used to construct an autocorrelation matrix which is used in the solution of the normal equations to find the required coefficients. Leaving out the scaling factor in the immediately above equation, the required autocorrelation function rxx(n), truncated to p samples, is defined as:                                           r            xx                    =                                                                      sin                  ⁡                                      (                                          n                      ⁢                                                                                           ⁢                      θ                                        )                                                                    n                  ⁢                                                                           ⁢                  θ                                            ⁢                                                           ⁢              n                        =            0                          ,        …        ⁢                                   ,                  p          -          1                                    Equation        ⁢                                   ⁢        12            
The normal equations are defined as:                                                         r              xx                        ⁡                          (              m              )                                =                                                    ∑                                  k                  =                  1                                p                            ⁢                                                a                  ⁡                                      (                    k                    )                                                  ⁢                                                      r                    xx                                    ⁡                                      (                                          m                      -                      k                                        )                                                  ⁢                                                                   ⁢                m                                      =            1                          ,        2        ,        …        ⁢                                   ,        p                            Equation        ⁢                                   ⁢        13            
This system of equations can be compactly written in matrix form by first defining several matrices.
To design a p-tap error predictor filter first compute a sinc function consisting of p+1 samples and construct the autocorrelation matrix Rxx as:                               R          xx                =                  [                                                                                          r                    xx                                    ⁡                                      (                    0                    )                                                                                                                    r                    xx                                    ⁡                                      (                    1                    )                                                                              …                                                                                  r                    xx                                    ⁡                                      (                                          p                      -                      1                                        )                                                                                                                                            r                    xx                                    ⁡                                      (                    1                    )                                                                                                                    r                    xx                                    ⁡                                      (                    0                    )                                                                              …                                                                                  r                    xx                                    ⁡                                      (                                          p                      -                      2                                        )                                                                                                      ⋮                                            ⋮                                            ⋮                                            ⋮                                                                                                          r                    xx                                    ⁡                                      (                                          p                      -                      1                                        )                                                                                                                    r                    xx                                    ⁡                                      (                                          p                      -                      2                                        )                                                                              …                                                                                  r                    xx                                    ⁡                                      (                    0                    )                                                                                ]                                    Equation        ⁢                                   ⁢        14            
Next, define a filter coefficient row-vector A as:A=[a(0), a(1), . . . , a(p−1)]  Equation 15 where a(i), i=0, . . . , p−1, are the predictor filter coefficients. Let the row-vector Rxx′ be defined as:Rxx′=[rxx(1), rxx(2), . . . , rxx(p)]  Equation 16 The matrix equivalent of equation 13 is:RxxAT=(Rxx′)T  Equation 17 The filter coefficients are therefore given as:AT=Rxx−1(Rxx′)T  Equation 18 
For the case in-hand, the solution of equation 18 is an ill-conditioned problem. To arrive at a solution for A, a small constant ε is added to the elements along the diagonal of the autocorrelation matrix Rxx in order to raise its condition number. The actual autocorrelation matrix used to solve for the predictor filter coefficients is:                               R          xx                =                  [                                                                                                                r                      xx                                        ⁡                                          (                      0                      )                                                        +                  ɛ                                                                                                  r                    xx                                    ⁡                                      (                    1                    )                                                                              …                                                                                  r                    xx                                    ⁡                                      (                                          p                      -                      1                                        )                                                                                                                                            r                    xx                                    ⁡                                      (                    1                    )                                                                                                                                          r                      xx                                        ⁡                                          (                      0                      )                                                        +                  ɛ                                                            …                                                                                  r                    xx                                    ⁡                                      (                                          M                      -                      2                                        )                                                                                                      ⋮                                            ⋮                                            ⋮                                            ⋮                                                                                                          r                    xx                                    ⁡                                      (                                          p                      -                      1                                        )                                                                                                                    r                    xx                                    ⁡                                      (                                          p                      -                      2                                        )                                                                              …                                                                                                        r                      xx                                        ⁡                                          (                      0                      )                                                        +                  ɛ                                                              ]                                    Equation        ⁢                                   ⁢        19            Bandpass Predictor Filter
The previous section described the design of a lowpass predictor. In this section, bandpass processes are considered.
A bandpass predictor filter is designed by modulating a lowpass prototype sinc function to the required center frequency θ0. The bandpass predictor coefficient hBP(n) is obtained from the prototype lowpass sinc function hLP(n) as:sincBP(n)=sincLP(n)cos(θ0(n−k)) n=0, . . . , 2p  Equation 20 where   k  =            [                                    2            ⁢                                                   ⁢            p                    +          1                2            ]        .  Highpass Predictor Filter
A highpass predictor filter is designed by highpass modulating a lowpass prototype sinc function to the required corner frequency θc. The highpass predictor coefficients hHP(n) are obtained from the prototype lowpass sinc function hLP(n) as:sincHP(n)=sincLP(n)(−1)n−k n=0, . . . , 2p  Equation 21 ΣΔ Modulator FPGA Implementation
The most challenging aspect of implementing the data modulator is producing an efficient implementation for the prediction filter P(z). The desire to support high-sample rates, and the requirement of zero latency for P(z), will preclude bit-serial methods from this problem. In addition, for the sake of area efficiency, parallel multipliers that exploit one time-invariant input operand (the filter coefficients) will be used, rather than general variable-variable multipliers. The constant-coefficient multiplier (KCM) is based on a multi-bit inspection version of Booth's algorithm. Partitioning the input variable into 4-bit nibbles is a convenient selection for the Xilinx Virtex function generators (FG). Each FG has 4 inputs and can be used for combinatorial logic or as application RAM/ROM. Each logic slice in the Virtex logic fabric comprises 2 FGs, and so can accommodate a 16×2 memory slice. Using the rule of thumb that each bit of filter coefficient precision contributes 5 dB to the sidelobe behavior, 12-bit precision is used for P(z). 12-bit precision will also be employed for the input samples. There are 3 4-bit nibbles in each input sample. Concurrently, each nibble addresses independent 16×16 lookup tables (LUTs). The bit growth incorporated here allows for worst case filter coefficient scaling in P(z). No pipeline stages are permitted in the multipliers because of P(z)'s location in the feedback path of the modulator.
It is convenient to use the transposed FIR filter for constructing the predictor. This allows the adders and delay elements in the structure to occupy a single slice. 64 slices are required to build the accumulate-delay path. The FPGA logic requirements for P(z), using a 9-tap predictor, is Γ(P(z))=9×40+64=424 CLBs. A small amount of additional logic is required to complete the entire ΣΔ modulator. The final slice count is 450. The entire modulator comfortably operates with a 113 MHz clock. This clock frequency defines the system sample rate, so the architecture can support a throughput of 113 MSamples per second. The critical path through this part of the design is related to the exclusion of pipelining in the multipliers.
Reduced Complexity FIR Mechanization
Now that the input signal is available as a reduced precision sample stream, filtering can be performed using area-optimized hardware. For the reasons discussed above, 4-bit data samples are a convenient match for Virtex devices. FIG. 13 shows the structure of the reduced complexity FIR filter. The coded samples {circumflex over (x)}(n) are presented to the address inputs of N coefficient LUTs. In accordance with the modulated data stream precision, each LUT stores the 16 possible scaled coefficient values for one tap as shown in FIG. 14. An N-tap filter requires N such elements. The outputs of the minimized multipliers are combined with an add-delay datapath to produce the final result. The logic requirement for the filter is Γ(H(z))=NΓ(MUL)+(N−1)Γ(ADD_z−1) where Γ(MUL) and Γ(ADD_z−1) are the FPGA area cost functions for a KCM multiplier and an add-delay datapath component respectively.
Using full-precision input samples without any ΣΔM encoding, each KCM would occupy 40 slices. The total cost of a direct implementation of H(z) is 7672 slices. The reduced precision KCMs used to process the encoded data each consume only 8 slices. Including the sigma-delta modulator the slice count is 3002 for the ΣΔ approach. So the data re-quantization approach consumes only 39% of the logic resources of a direct implementation.
ΣΔ Decimators
The procedure for re-quantizing the source data can also be used effectively in an m:1 decimation filter. An interesting problem is presented when high input sample rates (≧150 MHz) must be supported in FPGA technology. High-performance multipliers are typically realized by incorporating pipelining in the design. This naturally introduces some latency in to the system. The location of the predictor filter P(z) requires a zero-latency design. (It is possible that the predictor could be modified to predict samples further ahead in the time series, but this potential modification will not be dealt with in the limited space available.) Instead of re-quantizing, filtering and decimating, which would of course require a ΣΔ modulator running at the input sample rate, this sequence of operations is re-ordered to permit several slower modulators to be used in parallel. The process is performed by first decimating the signal, re-quantizing and then filtering. Now the ΣΔ modulators operate at the reduced output sample rate. This is depicted in FIG. 15. To support arbitrary center frequencies, and any arbitrary, but integer, down-sampling factor m, the bandpass decimation filter employs complex weights. The filter weights are of course just the bandpass modulated coefficients of a lowpass prototype filter designed to support the bandwidth of the target signal. Samples are collected from the A/D and alternated between the two modulators. Both modulators are identical and use the same predictor filter coefficients. The re-quantized samples are processed by an m:1 complex polyphase filter to produce the decimated signal. Several design options are presented once the signal has been filtered and the sample rate lowered. FIG. 15 illustrates one possibility. Now that the data rate has been reduced, the low rate signal is easily shifted to baseband with a simple, and area efficient, complex heterodyne. One multiplier and a single digital frequency synthesizer could be time shared to extract one or multiple channels.
It is interesting to investigate some of the changes that are required to support the ΣΔ decimator. The center frequency of the prediction filter should be designed to predict samples in the required spectral region in accordance with the output sample rate. For example, consider m=2, and the required channel center frequency located at 0.1 HZ, normalized with respect to the input sample rate. The prediction filter should be designed with a center frequency located at 0.2 Hz. In addition, the quality of the prediction should be improved. With respect to the output sample rate, the predictors are required to operate over a wider fractional bandwidth. This implies more filter coefficients in P(z). The increase in complexity of this component should be balanced against the savings that result in the reduced complexity filter stage to confirm that a net savings in logic requirements is produced. To more clearly demonstrate the approach, consider a 2:1 decimator, a channel center frequency at 0.2 Hz and a 60 dB dynamic range requirement.
FIG. 16(a) shows the double-sided spectrum of the input test signal. The input signal is commutated between τΔ0 and ΣΔ0 to produce the two low-precision sequences {circumflex over (x)}0(n) and {circumflex over (x)}1(n). The respective spectrums of these two signals are shown in FIGS. 16(b) and 16(c). The complex decimation filter response is defined in FIG. 16(d). After filtering, a complex sample stream supported at the low output sample rate is produced. This spectrum is shown in FIG. 16(e). Observe that the out-of-band components in the test signal have been rejected by the specified amount and that the in-band data meets the 60 dB dynamic range requirement. For comparison, the signal spectrum resulting from applying the processing stages in the order, re-quantize, filter and decimate is shown in FIG. 16(f). The interesting point to note is that while the dual ΣΔ modulator approach satisfies the system performance requirements, its out-of-band performance is not quite as good as the response depicted in FIG. 16(f). The stopband performance of the dual modulator architecture has degraded by approximately 6 dB. This can be explained by noting that the shaping noise produced by each modulator is essentially statistically independent. Since there is no coupling between these two components prior to S1 filtering, complete phase cancellation of the modulator noise cannot occur in the polyphase filter.